This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having wirings or electrodes of metal silicide and a method for manufacturing the same.
Recently, the requirements for the high integration density and high speed operation of semiconductor devices are increased. In order to meet the requirements, the distance between elements and the element size are reduced and studies for lowering the resistance of internal wiring materials are made.
A lowering in the resistance is a serious subject in the word line of a memory device in which the RC delay significantly appears. Therefore, recently, in order to reduce the resistance of the word line, a polycide gate formed of a 2-layered structure having a polysilicon film and a metal silicide film is widely used. Since the resistance of a refractory metal silicide film is lower than that of the polysilicon film by approximately one order of magnitude, the refractory metal silicide film may be desirably used as a material of a low resistance wiring. As silicide, tungsten silicide (WSi.sub.x) is most widely used.
However, in order to cope with a fine wiring of 0.15 .mu.m or less, it is required to further lower the resistance of the wiring so as to reduce the delay time. In order to realize the gate electrode having a low resistance of 1 .OMEGA./square or less by use of the polycide structure, silicide with a lower specific resistance is required.
As the low-resistance metal silicide, silicide of such as cobalt (Co) and nickel (Ni) is provided. However, since the halide of the above metals is low in the vapor pressure, it is extremely difficult to form the gate electrode by dry etching.
Therefore, when the above low-resistance metal silicide is used, the SALICIDE (Self Aligned Silicidation) technique is generally used. The technique is to deposit metal such as Co on the gate electrode and the source and drain regions and subject them to the heat treatment so as to selectively form silicide only on portions in which silicon is exposed. When the above technique is used, it is not necessary to subject the metal silicide to dry etching and it is possible to simultaneously form a silicide layer on the gate electrode and the source and drain regions.
On the other hand, with the progress of the miniaturization and high integration density, the requirement for the alignment precision of the exposure device becomes strict. Particularly, in a semiconductor memory as is represented by a DRAM, the integration density is high and the precision of alignment between the gate electrode and the contacts of the source or drain region is extremely severe.
Therefore, in order to solve the above problem, in the DRAM manufacturing process, the Self Aligned Contact (SAC) technique is used. The SAC technique is to surround the gate electrode with a silicon nitride film or the like and then form a contact hole by use of the high selectivity etching technique for a silicon oxide film against a silicon nitride film. By the SAC technique, even if the position of the contact is slightly deviated to the gate electrode side, the silicon nitride film is always present between the gate electrode and the contact, thereby preventing occurrence of an electrical short therebetween. Thus, the margin for the misalignment of the contact can be enhanced.
However, when the gate electrode is formed by use of the SALICIDE technique, it is impossible to previously cover the upper portion of the gate electrode with an insulating film for the sake of a step of forming metal silicide on the upper portion of the gate electrode. If the metal silicide is previously formed on the upper portion of the gate electrode and then an insulating film is formed on the metal silicide, formation of the contact hole cannot be effected in a self-alignment manner. That is, the SALICIDE technique and the Self Aligned Contact technique are incompatible. Therefore, it is extremely difficult to use the SALICIDE technique for a semiconductor device of high integration density such as a memory.
Moreover, if the low-resistance metal silicide of cobalt, nickel or the like is used for the gate electrode, it is extremely difficult to dry-etch the same into a desired shape. Therefore, it is considered to use the SALICIDE technique, but in this case, since it is incompatible with the Self Aligned Contact technique, it becomes extremely difficult to use the technique for the semiconductor device of high integration density.